Integration of ultra-thin 2D materials in future chips

Research centre imec is collaborating with chip manufacturers TSMC and Intel on an important step towards the future of chip technology: the integration and upscaling of 2D materials. These ultra-thin materials, only a few atomic layers thick, offer new opportunities to push the boundaries of chip miniaturisation.

At IEDM 1975, exactly 50 years ago, Gordon Moore - then at the head of chipmaker Intel - predicted that the number of transistors on a chip will double every two years. Since then, that prediction has become famous as Moore's Law and become a selffulfilling prophecy.

Physical limits

In the coming years, classical miniaturisation of silicon chips, driven by that Moore's Law, will hit physical limits. Transistors cannot become endlessly smaller without leakage currents and quantum effects interfering with operation. To continue meeting the growing demand for computing power - including for artificial intelligence - in the future, the industry is already searching for new materials and transistor architectures.

2D materials to the rescue?

One promising track is 2D materials. These materials are extremely thin - just one or a few atomic layers. This makes them promising as conduction channels in future chips, replacing the silicon channel that is increasingly difficult to shrink. But their great advantage also represents the great challenge at the same time: it is technically extremely difficult to apply such thin layers uniformly to silicon wafers and integrate them into existing production processes.

From lab to fab

Fifty years after Gordon Moore's famous presentation at IEDM, researchers from imec are presenting two papers at the same conference addressing the challenges surrounding 2D materials. In collaboration with TSMC, imec developed p-type transistors (pFETs) based on tungsten diselenide (WSe₂). These 2D transistors deliver record performance and are made with a process compatible with existing chip manufacturing, showing the potential of 2D materials for future chip architectures.

Integration of 2D materials

In parallel, imec worked on techniques enabling the integration of 2D transistors in industrial production. Indeed, until now, results were mainly limited to laboratory experiments on individual test chips. To make 2D materials industrially relevant, these processes need to be scaled up to 300mm wafers. This is the standard size of silicon wafers on which the industry mass-produces chips. In addition, reliability and uniformity must be guaranteed. Therefore, together with Intel, imec developed new techniques to integrate the basic components of 2D transistors (channel, contacts, gate and dielectric) more efficiently in mass production processes.

Optimisation needed

"Further optimisation is needed, but these new achievements show that it is possible to turn the promise of 2D materials into reality," he said. In collaboration with global players such as TSMC and Intel, imec is taking crucial steps towards industrial application of these materials," says Gouri Sankar Kar, vice president R&D compute & memory device technologies at imec.

Cleanroom of imec

At the beginning of this century, imec launched a pioneering 300 mm research programme. Since then, the cleanroom in Leuven, Belgium, has quickly become a key hub of the global semiconductor ecosystem. Here, the processes that will enable future microchip technology are jointly developed and perfected. To this end, the 8,000 m² cleanroom space is filled with the world's most advanced industry-relevant equipment - from all leading OEMs, including many European suppliers - for lithography, implantation, cleaning, metrology, deposition, etc.

Thanks to funding from the EU Chips Act, imec's 300 mm infrastructure has been expanded with a new cleanroom and dozens of additional advanced processing and metrology tools. This will take the efficiency of factory operations to the next level through more automation of tools, more connected instruments with central data storage and automated connections between repositories.

Photo: dust- and vibration-free laboratory at imec where the 2D materials are applied to 300mm wafers (photo: imec)
Source: imec

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